1. Field of the Invention
The present invention relates in general to integrated circuit (IC) testers and in particular to a tester having both analog and digital testing capability in each of its channels.
2. Description of Related Art
When an integrated circuit (IC) such as an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC) has both analog and digital input/output signals it has to be tested with an integrated circuit tester having both analog and digital channels. For example to test an ADC, the tester must supply an analog input signal to the ADC and monitor the sequence of digital output signals it produces to determine whether the ADC is properly digitizing its analog input signal. Conversely to test a DAC, the tester must supply a sequence of digital data values as input to the DAC and then monitor the DAC's analog output signal to determine whether it exhibits the behavior defined by the input data sequence.
FIG. 1 illustrates a typical general purpose IC tester including a set of N digital channels D1-DN and a set of M analog channels A1-AM for testing an ADC or DAC or other analog/digital device under test (DUT) 4. Each digital channel D1-DN may be connected to a separate digital I/O terminal of DUT 4 and may either supply a digital test signal input to that terminal or sample a digital DUT output signal produced at that terminal to determine its state. Each analog channel A1-AM may be connected to an analog DUT I/O terminal and may either supply an analog test signal input to the terminal or may digitize a DUT output signal at the terminal to produce a waveform data sequence representing the behavior of that DUT output signal. A "load board" 8 holds the DUT 4 during the test and provides traces 7 for routing signals between each DUT 4 I/O terminal and an appropriate digital channel D1-DN or analog channel A1-AM.
A test is organized into a succession of test cycles, and before the start of each test cycle each digital channel D1-DN needs a vector (a data value) to tell it what to do during the test cycle. The vector may, for example, tell the channel how and when to change the state of a test signal it supplies to a DUT 4 terminal during the test cycle, or may tell the channel to sample a digital DUT output signal generated at that terminal to determine whether it is of an expected state. Each analog channel A1-AM also needs data to tell it what to do during a test. For example if an analog channel is to generate an analog test signal, the channel requires a data sequence telling it how the analog test signal is to vary with time during the test. When an analog channel is to digitize an analog DUT output signal, it requires data telling it when to sample the output signal.
Before the start of a test a host computer 2, connected to all digital and analog channels D1-DN and A1-AM via a bus 10, sends the necessary vectors and programming data to each digital and analog channel. Thereafter host computer 2 sends a START signal concurrently to all channels telling them to begin the test. The channels D1-DN and A1-AM then begin performing the test activities defined by their input vectors and control data, synchronizing their activities to a master clock signal (CLOCK) produce by a clock source 9.
Since a test can span millions of test cycles, and since each digital channel D1-DN must store vector data to define its test activities for each test cycle, a vector memory within each digital channel that stores that data must be relatively large. One way to minimize the size of the vector memory is to keep the number of bits in each vector as small as possible while still providing a sufficient number of bits to distinguish between the various kinds of test events and event times that a vector may select. In order to keep a vector small, it has to be efficiently encoded. In a typical tester, vectors are of fixed size and certain fields of a digital channel vector are reserved for indicating the action the channel is to take, while other fields of the vector are reserved for indicating times during a cycle at which the channel is to take the actions. There is an inherent waste in such fixed allocation system for vector fields when the range of test activities and timing carried out by a channel during a test is relatively smaller than the range of activities and times that can be defined by a fixed length vector with reserved fields. It would therefore be beneficial if a tester could dynamically select vector size and assign meaning to each vector value to match the requirements of the test to be performed.
A general purpose tester with both analog and digital channels will typically not be able to use all its channel memory resources during any particular test. For example when testing a purely digital DUT, none of the analog channels are needed, or when testing a purely analog DUT, none of the digital channels are needed. Thus depending on the type of DUT being tested, much of the channel memory and other resources of the tester remain idle. If a tester could more flexibly allocate its resources, particularly its memory resources, it could perform longer and more complicated tests. For example, if a test requires digital channels only, it would be helpful if memory resources of the idle analog channels could in some way be made available to the digital channels so that they could store longer vector or instruction sequences.
It is helpful to position the channels as close as possible to the DUT so that DUT input and output signals do not have far to travel over load board routing paths 7 between the channels and the DUT terminals. Short signal paths help to reduce signal distortion and allow tests to be performed at higher signal frequencies. Since the tester architecture of FIG. 1 includes both the analog and digital channels, and since each channel requires a certain amount of space in the tester, it is difficult to position them as closely to the DUT as in a tester employing only digital channels. Thus load board 8 requires relatively longer signal routing paths 7. For this reason a general purpose tester having both analog and digital channels is unable to perform purely digital tests at as high a frequency as a similar tester having only digital channels. It would therefore be beneficial to provide an architecture for a general purpose analog/digital tester that minimizes the amount of space required by its channels.
Since a general purpose analog/digital tester must be able to test DUTs having a wide variety of analog and digital pin arrangements, it is not possible to know how best to configure the tester's channels. We do not know how to best allocate resources between analog and digital channels and we do not know how to best position analog and digital channels so as to minimize signal path distances. A test channel configuration that may be optimal for one DUT pin arrangement will not be optimal for a DUT having a different pin arrangement. It would therefore be beneficial to provide a tester in which channel configuration is substantially optimized for all DUT pin arrangements.
When it is necessary to perform a sequence of tests on DUT 4, host computer 2 must reprogram the channels after each test of the sequence. Since host computer 2 may have to send a large amount of data to the channels over bus 10 in order to reprogram them, such reprogramming effort between tests often requires substantially more time than the tests themselves. This reprogramming time substantially limits the throughput of a tester. It would be beneficial to provide a tester that can perform a sequence of digital/analog tests without having to be reprogrammed between tests.
What is needed is an integrated circuit tester capable of having both digital and analog signals, that minimizes signal routing distances between the tester and DUT and which makes efficient use of memory resources.